Stress-induced leakage currents of the RF sputtered Ta2O5 on N-implanted silicon

The electrical (C–Vand I–V) and reliability (constant current stress technique) properties of RF sputtered 30 nm thick Ta2O5 on N-implanted Si have been investigated. The dependence on the parameters of both Ta2O5 and the implanted interfacial layers on the stress time are discussed. The leakage current characteristics are analyzed by previously proposed comprehensive model. It is established that the reliability of the Ta2O5-based capacitors can be effectively improved if the Si substrate is a subject to preliminary N-implantation—markedly smaller stress induced leakage current as compared to the films on bare Si are detected. The stress mainly affects the properties of the interfacial layer and the generation of neutral traps is identified to be the primary cause for the stress-induced degradation. It is concluded that the implantation results in a strengthening of the interfacial layer against stress degradation.