Electrical characterization of high-k gate dielectrics on semiconductors

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) inelastic electron tunneling spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.