Title of article
Simultaneous routing and buffering in SOC floorplan design
Author/Authors
J.P.، Fang, نويسنده , , Y.-S.، Tong, نويسنده , , S.J.، Chen, نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2004
Pages
-16
From page
17
To page
0
Abstract
An EDA tool to deal with the problems of routing and buffer-insertion in system-on-chip floorplanning simultaneously is developed. This routing and buffering tool mainly consists of a Manhattan routing (MR) algorithm and a maze-based betweenbuffer routing algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution.
Keywords
Distributed systems
Journal title
IEE Proceedings and Digital Techniques
Serial Year
2004
Journal title
IEE Proceedings and Digital Techniques
Record number
106222
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