Design and analysis of up-down counters

Several designs for an up-down N-counter are derived for any N > 0. The up-down N-counter has a simple specification, but allows many non-trivial, efficient implementations. All designs are represented by means of a CSP-like program and are analyzed with respect to area, response time, and power consumption. Our final design has optimal area of Θ(log N), a bounded response time, and a bounded power consumption.