Overview on a formal model of architecture/circuit trade-offs for the implementation of fast processors Original Research Article

Implementation complexity is playing an increasingly important role in the development of high-speed microprocessors, in terms of limitations to the actual cycle time. It is useful for the CPU architecture designer to have an assessment of the achievable cycle time when making architecture design decisions. Formal models exist that allow the designer to have an accurate estimation of the best possible delay of logic units before doing circuit and layout design. The combination of such modeling techniques together with instruction-level cycle-accurate simulation of the CPU architecture can be a powerful tool for the development of fast processors.