ESD-level circuit simulation impact of interconnect RC-delay on HBM and CDM behavior

An extraction method for the distributed, parasitic RC-elements of MOS single- and multi-fingers is introduced by deducing a rule of thumb for an effective poly resistance Reff. The lumped RC element described by the effective gate resistance in conjunction with the non-linear gate capacitance of the MOS model Cgate approximates sufficiently accurate the distributed RC elements of the gate in the ESD relevant time domain. In addition to the wiring and parasitic capacitance connected to a gate, this RC can cause a significant gate delay (RC∼1 ns) during ESD events. It is demonstrated for a CMOS output driver circuit that this effect is relevant for ESD switching behavior under human body model (HBM) stress. Here, circuit simulations are compared to the corresponding transmission line pulse (TLP) measurements. Furthermore, a general charge device model (CDM)-level circuit simulation methodology is presented. To our knowledge for the first time, a single-pin CDM event was simulated in a complex I/O circuit applying appropriate ESD models suitable for CDM simulation. Under such stress, the simulation reveals an unexpected large impact of the ‘gate’ RC-delay formed by metal interconnects in a CMOS double input inverter. Voltage overshoots occur at internal gates and lead to oxide breakdown. The failure signature was validated by CDM stress tests and physical failure analysis.