The application of transmission line pulse testing for the ESD analysis of integrated circuits

Transmission line pulse (TLP) testing is well known for device characterisation in ESD circumstances. In this paper TLP is applied to full-integrated circuits and is shown to offer valuable data for the analysis of the ESD behaviour of ICs. TLP is the only method to study ESD behaviour during ESD stressing and as such provides essential knowledge about actual ESD current paths. The paper shows that both TLP characteristics and recordings of the actual waveforms should be used for a correct analysis. As illustrated by several examples, from different design groups and from different processes, such analysis gives valuable suggestions for improving circuit designs.