An automated design system methodology and strategy for electrostatic discharge protection circuits in RF CMOS and BiCMOS silicon germanium technology ☆

In a Cadence environment, a novel automated methodology is established to optimize (electrostatic discharge) ESD networks. An automated ESD design system for digital, analog and radio frequency (RF) circuits in a mixed signal semiconductor chips using a hierarchy of RF-characterized higher order graphical parameterized cells allows for co-synthesis of RF design and ESD evaluation. The auto-generated ESD design system includes CMOS and BiCMOS input, rail-to-rail and power clamp ESD network with layout, schematic and symbolic representations. Human body model (HBM), machine model (MM), and transmission line pulse (TLP) results demonstrate the operation of the ESD designs, and the region of optimum ESD results.