• Title of article

    Stress-induced voiding in stacked tungsten via structure

  • Author/Authors

    Domae، Shinichi نويسنده , , Eto، Ryuji نويسنده , , Okuma، Keiji نويسنده ,

  • Issue Information
    روزنامه با شماره پیاپی سال 1999
  • Pages
    -506
  • From page
    507
  • To page
    0
  • Abstract
    The stress-induced voiding (SV) in Al-alloy films with stacked tungsten via structures was investigated. Voids were found in interconnections with stacked and borderless vias that had resistance increase after the aging tests. Failure occurs most frequently when the test structures are stored at approximately 25(degree)C. This behavior can be explained by the diffusion creep model similar to SV in a flat line [1]. Finite-element simulations show that tensile stress in Allines between upper and lower plugs increases with temperature increase over 175(degree)C. Al grains on W-plugs were found to have high-angle crystalline misorientation in transmission electron microscopy (TEM) observation. The tensile stress and grain misorientation should accelerate the void growth during high temperature storage. 02 plasma post metal etch treatment is effective to eliminate SV in stacked via structure. (C) 1999 Elsevier Science Ltd. All rights reserved.
  • Keywords
    Extrapolation , Finite element method , Chip Scale Package , Solder fatique , Creep , Viscoplasticity , Viscoelasticily
  • Journal title
    MICROELECTRONICS RELIABILITY
  • Serial Year
    1999
  • Journal title
    MICROELECTRONICS RELIABILITY
  • Record number

    12945