Analysis of stresses and breakage of crystalline silicon wafers during handling and transport

A significant challenge in using thinner and larger crystalline silicon wafers for solar cell manufacture is the reduced yield due to higher wafer breakage rates. At a given process step, wafer/cell breakage depends on the stresses produced in the wafer/cell due to prior processing, handling and/or transport and on the presence of structural defects such as cracks. Specifically, analysis of wafer breakage requires knowledge of the total in-plane stress state produced in the wafer due to handling and residual stresses from prior processing. This paper presents a systematic approach to breakage analysis of crystalline silicon wafers during handling via analysis of the total stress state produced in the wafer. The total stress state is determined using a combination of wafer deformation measurements and non-linear finite element analysis. Knowledge of the total stress state in conjunction with the crack size and location enables the determination of wafer breakage and the associated fracture stress. This approach is experimentally validated through breakage tests performed on edge-defined film-fed growth (EFG) wafers with cracks introduced via indentation. The results show that the wafer breakage stress during handling is proportional to the inverse of the square root of the crack length, which is consistent with the linear elastic fracture mechanics theory. The work also confirms the capability of the proposed approach to determine the handling conditions under which wafer/cell breakage will occur.