Optimization of IC encapsulation considering fluid/structure interaction using response surface methodology

Optimized design of the integrated circuit (IC) package gives better IC encapsulation process and minimizes the stress concentration and deformation of the IC structures. The physical and process parameters (i.e., pressure inlet, solder bump standoff height, chip thickness, gap-wise between chips, and mould and filled time) were optimized via response surface methodology using central composite design (CCD) to minimize the stress concentration of chip and solder bump, chip deformation, and void in package during the IC encapsulation process. The optimization of the moulded IC encapsulation is carried out by considering the fluid/structure interaction (FSI) aspects. The optimum empirical models were tested and well confirmed with the simulation results. The optimum design of the IC package (20 mm × 20 mm) with perimeter solder bump arrangement for both physical and process parameters was characterized by 150 μm of solder bump standoff height, 250 μm of chip thickness, and 50.43 μm of gap-wise at the inlet condition of 3.43 MPa.