An improved Elmore delay model for VLSI interconnects

Elmore delay metric is a widely used model to compute signal delays for both analog and digital circuit interconnects. Although it provides a limited accuracy and its applicability is limited to the step function type input signals, this model is extremely popular with simple analytical functions that can be easily incorporated into design and automation software. In this work, a new boundary limiting the Elmore delay is introduced. A general form of traditional Elmore delay is defined and solved by utilizing this boundary. The new solution of the propagation delay problem called the improved Elmore delay model is derived according to the compound interest problem of Jacob Bernoulli. The improved Elmore delay formulation and the traditional Elmore delay model are compared according to SPICE simulation environment performances which verifies the superior accuracy of the novel delay formulation. The test results proved that better accuracy is achieved with the improved Elmore delay model than the traditional Elmore delay model with the same computation speed.