Design of a 3GPP turbo decoder using SW-BCJR algorithm with small memory block

Turbo code with its performance close to the Shannon limit has been received a lot of interest for many applications. SW-MAP algorithm, a decoding scheme of the turbo code has a lot of advantage in the amount of memory storing the metric value, and in the operation performance with a small increase of calculation compared with the conventional MAP scheme. A turbo decoder complying with 3GPP specification is proposed. The structure of the decoder is modified to reduce the amount of memory of the input buffer, the metric memory, the interleaver and the deinterleaver though it is based on the SW-MAP scheme. The amount of memory is reduced by about 50% of the conventional SW-MAP decoding scheme using an address generation control scheme.