A dual band CMOS VCO with a balanced duty cycle buffer

This paper proposes a dual band VCO with a standard 0.35 μm CMOS process to generate 1.07 and 2.07 GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder (HA) is able to produce a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561 MHz/V and 14.6 mW, respectively. The phase noises of the dual band VCO are measured to be −102.55 and −95.88 dBc/Hz at 2 MHz offset from 1.07 and 2.07 GHz, respectively.