The fabrication of advanced transistors with plasma doping

Plasma doping (PLAD) has recently been developed to become a reliable doping technology for the silicon industry. The extreme difficulty of implanting the doping species at the very low energy required by very advanced transistor technology (sub-0.1 μm) by standard ion implantation is strong motivation for device manufacturers to explore alternative doping technology, such as PLAD. In this paper, we show how we have used the PLAD technique to improve the ultra-shallow junction (USJ) process formation and the USJ characteristics. We have integrated this process into a very advanced industrial complementary metal-oxide semiconductor (CMOS) process flow. The electrical performance of p-type metal–oxide semiconductor field-effect transistors (pMOSFETs) fabricated by PLAD or ion implantation is compared. We show that the benefit of using the PLAD technique is increased as the transistors are shrunk from 0.18 down to 0.09 μm.