Router Architecture for Network on Chip Using FPGA

On Single chip integration of storage and computational block has becoming feasible due to continuous shrinkage of CMOS technology [1]. Field programmable gate arrays (FPGA’s) are power efficient devices [3] support more complex design with good performance and low cost [6]. For effective global on-chip communication, on-chip routers provide essential routing functionality with low complexity and relatively high performance [1]. Routers implemented within FPGA can give better performance with reduced area and hence reduced power consumption [4]. This paper will provide an overview of related work for on-chip router architectures.