Recent advances in nanoparticle memories

Nanoparticle memories have made their point during last years as a possible solution to overcome the scaling issue of electronic non-volatile memories. Ultimately, we are looking for nanoparticle memories to significantly decrease the voltage needed to write/erase the memory without compromising its retention characteristics. Several approaches have been reported for semiconductor nanoparticle formation using techniques such as chemical vapor deposition, molecular beam epitaxy or sputtering. In the present review emphasis is placed on a silicon nanoparticle memory resulting from low-energy ion implantation of silicon within a thin oxide layer and subsequent annealing. This process allows for the formation of a two-dimensional array of silicon nanoparticles within the gate oxide in one processing step making the process attractive for CMOS integration. Material issues related with ion implantation energy, dose and annealing ambient for optimum device performance are addressed. As an alternative to semiconductor nanoparticles, metallic nanoparticles have been investigated since they have the potential for more versatile engineering of energy barriers that would allow improved data retention for memory devices operating at low voltages. Processing approaches for metallic nanoparticle formation are addressed and corresponding memory device performance is discussed for the particular case of room temperature deposited metallic nanoparticles by chemical methods.