Application of high-k dielectric stacks charge trapping for CMOS technology

The effect of constant negative voltage stress on charge trapping and interface states of Al/HfO2/SiOxNy/Si structures are investigated. The reduction in the capacitance of C–t characteristics and a significant shift in C–V curves towards negative voltage axis reveal that the charge trapping/detrapping occurs at the Si/SiOxNy/HfO2 interface and HfO2 bulk. However, there is a relative increase in gate leakage current as a function of the voltage stress and time, owing to the trap-assisted tunnelling. It is suggested that these traps are probably Hf–OH neutral centers, originating from the breaking of bridging Si–OH and Si–NH bonds by mobile H+ protons. This has potential application in non-volatile CMOS memory devices.