Virtual prototype method used in design of electronic circuitry for CDF

The use of powerful CAE/CAD tools allows designers to substantially reduce development time and costs of complex electronic circuitry such as 9U VME Boards used in the CDF experiment. We describe a method implemented to design and fully simulate circuit boards used in the CDF experimentʹs Level 1, Level 2, and Silicon Tracker (SVT) trigger, considering both the functional and the signal integrity issues. Integrating Synopsys and Altera CAD tools in a Mentor Graphics design environment permits an accurate connector-to-connector or even multi-board functional simulation, which includes the placement and layout effects. This method of evaluating the whole circuit board in a comprehensive simulation process has greatly reduced design and implementation time.