Improved coincidence rejection for silicon drift detectors

The high count rates possible with silicon drift detectors (SDDs) raise the importance of coincidence (“pile-up”) rejection in the pulse processor. Detection efficiency for close coincidence is energy dependent, with resolving times increasing sharply when at least one X-ray of the pair is below 1 keV. Traditional pile-up detection for low energies is done by applying a width test to the output of a shaping filter. SDDs have varying rise times at the preamplifier output due to the expansion of the charge cloud with drift path length, which limits the effectiveness of pulse width testing. Novel digital methods have been developed, which are largely immune to variations in rise time and significantly improve pulse-pair resolving times. Digital pulse processor filter parameters must take resolving times into account to achieve good sum peak position and shape for optimum software removal of sum peak artifacts during spectrum post-processing.