Test results of a self-triggering silicon strip detector readout chip

The n-XYter integrated circuit (ASIC) was designed in a CMOS 0.35 μm technology, as a 128-channel, data-driven silicon detector readout chip and became a prototype readout chip for several experiments at the Facility for Antiproton and Ion Research (FAIR). The details of the circuit architecture have already been published [C. Schmidt, et al., in: Proceedings of the Topical Workshop on Electronics for Particle Physics, Prague, Czech Republic, 03–07 September 2007; A. Brogna, et al., Nucl. Instr. and Meth. A 568 (2006) 301]. In this paper we present test results on discriminator threshold spread and its correction, analogue front-end gain measurements and calibration of the time-stamp circuitry. The measurements were performed using on-chip test pulses. The ASIC was connected to a 1 cm long, 100 μm pitch, AC-coupled silicon strip detector (SSD).