Minimizing makespan in a flow-line manufacturing cell with sequence dependent family setup times

The flow-line manufacturing cell scheduling problem (FMCSP) with sequence dependent family setup times (SDFSTs) is a topic of great concern for many industrial applications, but under-represented in the research literature. In this study, a two-level iterated greedy (TLIG) heuristic is proposed to minimize makespan of this strongly NP-hard problem. The performance of the proposed TLIG heuristic is compared against eight existing algorithms on a benchmark problem set used in earlier studies. The experimental results reveal that the proposed TLIG heuristic is very effective and efficient at finding near-optimal solutions for FMCSPs with SDFSTs.