Reducing the Power Consumption in Flash ADC using 65nm CMOS Technology

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreased power consumption by approximately 90% for different processing corners. In addition, in this paper the proposed method is designed using an interpolation technique for the purpose of promoting the performance as well as decreasing the class of Chip. The simulation results indicate that the power consumption for the interpolation technique is decreased by approximately 5% compared to the proposed method. On the other hand, we compare the results of the proposed convector with those of convertors frequently referred in other studies. Also, the results show that the power consumption is considerably decreased, using the proposed method.