A Comprehensive and Comparative Study on Online Testability for Reversible Logic

Reversible logic is one of the rising fields for low-power electronic devices. Testing of these devices is a significant issue where the researchers are at par with the latest innovations in the field. However, new technology gives birth to new challenges, and in this field too, several fault models have arisen. Several online testing methods have been proposed for their detection, which are scaled on various performance parameters. This paper provides a comparative study of online testability for reversible logic. We bring together a review of fault models, performance parameters and online testing strategies from the literature with the aim of obtaining a near optimal solution by efficiently exploring the entire search space. We critically analyze a range of online testing strategies reported by researchers using parity preservation and generation, dual-rail coding and concurrent error detection schemes. These strategies are presented in two broad classifications, namely designing with novel gates and designing with existing circuits. All the techniques are explained in detail with a brief mathematical illustration. A comparison of experimental results based on the available number of benchmarks and combinational logic circuits is presented. The best possible strategy is highlighted on behalf of performance parameters.