A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology

In this paper, a new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on capacitor merged technique is presented. The main goal of the proposed idea is to achieve high-resolution and high-speed SAR ADC, simultaneously. It is noteworthy that, exerting the suggested method, the total capacitance and the ratio of the MSB and LSB capacitors are decreased; as a result, the speed and accuracy of the ADC are increased reliably. Therefore, applying the proposed idea, it is reliable that to attain a 12-bit resolution ADC at 76MS/s sampling rate. Furthermore, the power consumption of the proposed ADC is 694µW with the power supply of 1.8 volts correspondingly. The proposed post-layout SAR ADC structure is simulated in all process corner conditions and different temperatures of -50? to +50?, and performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.