Secure FPGA Design by Filling Unused Spaces

There are di erent kinds of attacks on Field Programmable Gate Array (FPGA). As FPGAs are used in many di erent applications, its security becomes an important concern, especially in Internet of Things (IoT) applications. Hardware Trojan Horse (HTH) insertion is one of the major security threats that can be implemented in unused space of the FPGA. This unused space is unavoidable to meet the place and route requirements. In this paper, we introduce an e cient method to ll this space and thus leaving no free space for inserting HTHs. Using a shift register in combination with gate-chain is the best way of lling unused space, which incurs a no increase in power consumption of the main design. Experimental results of implementing a set of IWLS benchmarks on Xilinx Virtex devices show that the proposed prevention and detection scheme imposes a no power overhead and no degradation to performance and critical path delay of the main design.