Title of article
Implementation of RADAR Quadrature Channel Receiver in FPGA
Author/Authors
Mahdlo Abdollah Department of Telecommunication and Information Technology - Imam Hossein University - Tehran, Iran , Alaee Mohammad Department of Electrical and Electronic Engineering - Isfahan University of Technology - Isfahan, Iran , khaleghei Bizaki Hossein Department of Electrical and Electronic Engineering - Malek Ashtar University of Technology - Tehran, Iran
Pages
6
From page
63
To page
68
Abstract
In this paper we have presented the implementation of radar digital quadrature channel receivers in FPGA. Utilizing direct digitalization due to avoid improbable matching in producing in-phase (I) and quadrature (Q) signals, is greatly respecting in every modern system but this merit needs some considerations which are highlighted in the current paper. Two factors resource and maximum frequency for hardware implementation of proposed algorithm utilizing Virtex-5 ML506 are evaluated and compared with the customary algorithm of analog and digital receivers which generally utilize two mixers, lowpass filters and analog to digital converters for down converting signal from intermediate frequency to baseband. Also in this paper some simulations for different examples are illustrated.
Keywords
IF sampling , FPGA , Digital quadrature channel receiver , Radar
Journal title
Majlesi Journal of Telecommunication Devices
Serial Year
2016
Record number
2514023
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