Title of article
Evaluation and Analysis of Packet-Length Effect on Networks-on-Chip
Author/Authors
JIN, Depeng Tsinghua University - Department of Electronic Engineering, China , LIN, Shijun Tsinghua University - Department of Electronic Engineering, China , LIN, Shijun Xiamen University - Department of Communication Engineering, China , SU, Li Tsinghua University - Department of Electronic Engineering, China , ZHOU, Guofei Tsinghua University - Department of Electronic Engineering, China , ZENG, Lieguang Tsinghua University - Department of Electronic Engineering, China
From page
288
To page
293
Abstract
The network-on-chip (NoC) design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency, and energy consumption. The appropriate NoC packet-length was selected based on simulation and analysis of the packet-length effect on NoC for variable average data block length (ADBL) configuration parameters. A trade-off curve among throughput, latency, and energy consumption was developed and shows that the optimum packet length increases as the ADBL increases.
Keywords
network , on , chip , system , on , chip , packet , length effect , MP , SoC
Journal title
Tsinghua Science and Technology
Journal title
Tsinghua Science and Technology
Record number
2535283
Link To Document