Title of article
Low-Power Adder Design for Nano-Scale CMOS (Short Paper)
Author/Authors
Talebiyan, S. R. ferdowsi university of mashhad - Department of Electrical Department, مشهد, ايران , Hosseini-Khayat, S. ferdowsi university of mashhad - Department of Electrical Department, مشهد, ايران
From page
180
To page
184
Abstract
A fast low-power l-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
Keywords
Nano , Scale CMOS Technology , Static Power Consumption , Adder Subcomponents
Journal title
Iranian Journal of Electrical and Electronic Engineering(IJEEE)
Journal title
Iranian Journal of Electrical and Electronic Engineering(IJEEE)
Record number
2551240
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