Formal Derivation of a Particular Input of a Single AND (OR) Gate in Terms of Its Output and Other Inputs

This note studies two dual problems that arise frequently in the probabilistic and testability analysis of combinational digital circuits and the a posteriori analysis of fault trees. These problems pertain to expressing a particular input of a single AND or (OR) gate in terms of its output and other inputs. We formally derive the required input, for each of the two dual cases, by finding the general parametric solution of an equivalent problem over a big Boolean algebra. The solutions obtained provide pedagogical insight and have direct interpretations in terms of substantially reduced truth tables. As an offshoot, this note confirms, by way of concrete examples, that the a ‘big’ Boolean algebra is both useful and unavoidable for engineering applications, and that truth tables do not have to be explicitly of exponential sizes, but might be compressed, when possible, to few lines only.