Modeling and Simulation of Finite State Machine Memory Built-in Self Test Architecture for Embedded Memories

Memory Built-in Self Test (MBIST) or as some refer to it array as built-in self-test is an amazing piece of logic. Without any (direct) connection to the outside world, a very complex embedded memory can be tested efficiently, easily and at lower cost. Modeling and simulation of Finite State Machine (FSM) MBIST is presented in this paper. The design architecture is written using Very High Speed Integrated Circuit Hardware Description Language (VHDL) code using Xilinx ISE tools. The architecture is modeled and synthesized using register transfer level (RTL) abstraction. Verification of this architecture is carried out by testing stuck-at-faults SRAM. Two BIST algorithms are implemented, i.e., MATS and March C-to test the faulty SRAM.