Fast Lock and Settling Time Improvement for Indirect Frequency Synthesizer Phase Locked Loop

Settling time is one of the major quality feature in phase locked loop frequency synthesizer (PLL-FS). Additionally, fast lock is very important for PLL in multiple applications. When PLL in lock range becomes as fast as possible, it gives no error in a comparison process; and the system works probably. In this paper, a new design of indirect Phase locked loop frequency synthesizer circuit is proposed to minimize the settling time at PLL-FS output signal when there is a sudden change in frequency. In this work, a great improvement is achieved to speed up the lock-in time of the circuit. The proposed design improves the settling time up to 80% at output frequency; and the lock- time speed is increased. ORCAD and MATLAB simulators are used to show the proposed design validity.