Improved binary rate multiplier

A new clock-controlled model that is built up from two feedback shift registers (FSRs) is introduced for use in stream cipher applications. The design of the introduced model is related to the so-called binary rate multiplier. It is simple and scalable, based on two LFSRs combined such that one controls the clocking of the other. The design provides the basic security requirements such as large period, high linear complexity and good statistical properties, and is resistant to known cryptanalytic attacks