• Title of article

    Modified cache template attack on AES

  • Author/Authors

    Esfahani, M. Department of Mathematics - Islamic Azad University Karaj Branch, Karaj, Iran , Soleimany, H. Cyberspace Research Institute - Shahid Beheshti University, Tehran, Iran , Aref, M.R. Department of Electrical Engineering - Sharif University of Technology, Tehran, Iran

  • Pages
    8
  • From page
    1949
  • To page
    1956
  • Abstract
    While it has been known for a long time that the cache behavior is a powerful source of the information leakage, more realistic attack scenarios have received a lot of attention by the cryptographic community. To develop practical cache-based attacks, there is an increasingly need to automate the process of finding exploitable cache-based side-channels in computer systems. Cache template attack is a generic technique that utilizes Flush+Reload attack in order to automatically exploit cache vulnerability of Intel platforms. Cache template attack on T-table-based AES implementation consists of two phases including the profiling phase and the key exploitation phase. Profiling is a preprocessing phase to monitor dependencies between the secret key and behavior of the cache memory. In addition, the addresses of T-tables can be obtained automatically. In the key exploitation phase, most significant bits (MSBs) of the secret key bytes are retrieved by monitoring exploitable addresses. In this paper, we propose a simple yet effective searching technique which accelerates the profiling phase by a factor of at most 64. To verify the theoretical model of our technique, we implement the described attack on AES. The experimental results confirmed a shorter runtime of the attack in comparison to the original attack.
  • Keywords
    Side-channel attacks , Flush+Reload attack , inclusive memory , AES , cache template attacks
  • Journal title
    Scientia Iranica(Transactions D: Computer Science and Electrical Engineering)
  • Serial Year
    2022
  • Record number

    2731577