A fast approximate quaternary full adder using a parallel design based on Carbon nanotube FET

Novel design methodologies of digital circuits have been caught in the spotlight of attention as a result of the dramatic increase in available data and the requirement for data processing among which Full adder cells are significant elements in arithmetic circuits design. The use of approximate computing and Multi Value Logic (MVL) can improve computational circuit efficiency. Carbon Nano Tube Field Effect Transistors (CNTFETs) with an adjustable threshold voltage is effective in the design of MVL circuits. This paper proposes a new CNTFET-based approximate quaternary full adder to reduce the area, delay, and power consumption. The Synopsys HSPICE results obtained based on 32nm Stanford CNTFET technology showed that the proposed model had much lower average power consumption, delay, power-delay product (PDP), and size as compared to other approximate full adders.