TOPS information processing on a single chip

One of the main objectives in CNN design is to have as small a cell size as possible and because there are normally 19 synapses implemented in each cell, we cannot select an architecture that is very area consuming. In our approach we simplify the multiplication procedure without losing the overall input-output mapping. In that way the synapses can be built from very few transistors and the cell layout can be made small. What has been noticed is that when the initial values of the network are bipolar and when the obtained network output is also bipolar, in almost every case we can use a high-gain output nonlinearity to replace the unity gain. Another required modification is to move the whole processing into a positive range