Taking a deep look at analog CMOS

When moving to deep-submicron design, the analog designer faces a number of challenges unique to that regime. Due to the need to decrease the supply voltage Vdd (due to power dissipation and hot carrier reliability concerns) while the threshold voltage Vt cannot be decreased (due to off-state power constraints), the analog designer is faced with a decrease in the available window for current swing above threshold (Vgs-Vt). In addition, in the deep-submicron regime the long-channel proportionality Ids∝(Vgs-Vt)2 becomes less favorable, reaching a short-channel limit of Ids∝(V gs-Vt). Taken together, these two factors reduce the voltage-controlled sensitivity that the designer can exercise over the FET; this is a desirable (controllable) sensitivity for the designer, and it hurts the designer to lose it in this way. On the other hand, in deep-submicron devices, the device characteristics become move sensitive to variations in the channel length, greatly complicating basic design tasks, as well as magnifying the effects of process variations and device mismatch. This is an undesirable (uncontrollable) sensitivity. Note that the desirable sensitivity decreases while the undesirable sensitivity increases. Furthermore, deep-submicron device behavior is very difficult to model accurately; analytical descriptions used for circuit simulation will inevitably introduce further error into the design effort. In addition, the extreme complexity of present-day analytical MOSFET descriptions that are employed for circuit simulation precludes their use in conventional analog design practice, where hand calculations, further manipulation of the model equations, and the ability to move back and forth between MOSFET “observables” (drain current, transconductance, etc.) and device aspect ratio are standard tools of the trade. These issues must be addressed in the development of future analytical MOSFET descriptions for circuit simulation