Modeling techniques for energy-efficient system-on-a-chip signaling

In order to tackle noise, delay, and power in the deep-submicron age, the most efficient approach is to design power-efficient and robust signaling techniques that allow for reliable communication between CMOS gates. This is referred to as energy-efficient on-chip-signaling. To design, optimize, and compare different signaling schemes, it is important to properly model on-chip wires. This article describes several techniques used in interconnect modeling. It focuses on the efficient modeling of on-chip wires, investigates the impact of inductive and capacitive coupling on the quality of the signal and the wire-load model, and contains a quantification of the impact of the wire model on the design of efficient signaling techniques.