An Educational Digital Communications Project Using FPGAs to Implement a BPSK Detector

With the recent advent of hardware description languages (e.g., Verilog or VHDL) and digital implementation for field-programmable gate arrays (FPGAs), substantial academic digital design projects become practicable. The time and effort to implement significant design projects may be undertaken without sacrificing the broad educational demands placed upon the modern engineering student. In the present paper, the design of an all-digital, binary-phase-shift-keying (BPSK) demodulator is described. The project details the design of the components (e.g., Booth multipliers and pseudorandom noise (PN) generators) and the simulation of the entire system. The entire system was designed using the Verilog hardware description language and implemented on an Altera 10-k FPGA device. This paper verifies that students are capable of accomplishing significant signal processing projects that provide educational benefits. Projects can readily be extended by developing several such projects across a class and then integrating distinct projects into more fully developed systems. The project described in this paper is the design and simulation of a BPSK correlation detector.