• Title of article

    Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses

  • Author/Authors

    Naran Sirisantana، نويسنده , , Intel Kaushik Roy، نويسنده , , Purdue University ، نويسنده ,

  • Issue Information
    روزنامه با شماره پیاپی سال 2004
  • Pages
    8
  • From page
    56
  • To page
    63
  • Abstract
    Two CMOS design techniques use dual threshold voltages to reduce power consumption while maintaining high performance. Simulation results show power savings of 21% for one technique at low activity, and for the other, 19% at high activity and 38% at tow activity.
  • Journal title
    IEEE Design and Test of Computers
  • Serial Year
    2004
  • Journal title
    IEEE Design and Test of Computers
  • Record number

    431469

    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=10&DC=431469