An Illustrated Methodology for Analysis of Error Tolerance

Noise, defects, and process variations are likely to cause very unpredictable circuit performance in future billion-transistor dies, hence decreasing raw yield. Error tolerance is one of several techniques that can increase effective yield. This article presents a methodology for analyzing the suitability of error tolerance for a particular application and implementation. The methodology, illustrated here by a digital telephone-answering device, is applicable to a broad class of systems.