A 1.5-V 50-MHz Pseudodifferential CMOS Sample-and-Hold Circuit With Low Hold Pedestal

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timingskew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-(mu) m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than 54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 V(pp) . In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 V(pp) full-scale differential input range are achieved.