A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories

A reference generation scheme is proposed for a 1T-1C ferroelectric random-access memory (FeRAM) architecture that balances fatigue evenly between memory cells and reference cells. This is achieved by including a reference cell per row (instead of per column) of the memory array. The proposed scheme converts the bitline voltage to current and compares this current against a reference current using a current-steering sense amplifier. This scheme is evaluated over a range of bitline lengths and cell sizes in a 16-Kb test chip implemented in a 0.35-/spl mu/m FeRAM process. The test chip measures an access time of 62 ns at room temperature using a 3-V power supply.