Survey On ASIC Design of High Speed Photo receiver Using 0.18um CMOS Technology

The current work focuses on the design of a fully integrated single beam photoreceiver that can accept optical pulses of 850nm wavelength at a bandwidth as high as 1Gbps. This is highly suitable for implementation in fiber optic LANs and short haul optical interconnects. The recent advances of fiber optic communication technology with VLSI circuit design methodologies has motivated the development of low power complementary metal oxide semiconductor (CMOS) photoreceiver capable of detecting optical pulses at 1Gbps. The receiver integrates a photo-detector and a diagnosis circuit. The idea of using the CMOS technology is to achieve a high speed low power implementation of the system. The average power dissipation of the receiver has been found earlier to be less than 0.105mW at a supply voltage of 1V for 0.3 ?m CMOS technology. The current work has been done using the 0.18?m CMOS technology with power dissipation as low as. Also, a comparative study of speed response of the receiver circuit has been made for different values of junction resistance and capacitance of the p-i-n photodiode. The whole work has been done using TSPICE simulation tool.