Integrated design of run-to-run PID controller and SPC monitoring for process disturbance rejection

An integrated design methodology has been developed for a run-to-run PID controller and SPC monitoring for the purpose of process disturbance rejection. In the paper, the process disturbance is assumed to be an ARMA (1,1) process. A detailed procedure is developed to design a PID controller which minimizes process variability. The performance of the PID controller is also discussed. Ajoint monitoring of input and output, using Bonferroniʹs approach, is then designed for the controlled process. The ARL performance is studied. One major contribution of the paper is to develop a complete procedure and design plots, which serve as tools to conduct all the aforementioned tasks. An example is provided to illustrate the integrated design approach.