Parallel digital neural hardware for controller design Original Research Article

A general comparison with regard to speed and size of digital neural hardware on different levels of parallelism results in the design of a fully parallel architecture based on a bit-serial neural hardware model with a new quadratic squashing function. This nonlinear squashing function is well suited for small parallel digital hardware implementations. A cascadable semicustom chip containing six neurons was designed based on this model. This neurochip is used in the hardware implementation of a neurocontroller. The controller is developed for the lateral control of a vehicle and trained from only 6000 samples of human driving behavior recorded on a German federal highway.