Technology for very dense hybrid detector arrays using electroplated indium solderbumps

This paper presents a detailed overview of the process steps involved in the hybrid integration process of III-V infrared detector arrays and silicon readout electronics. This process is divided in distinct parts: the postprocessing of the Silicon readout circuit, the Indium solderbump formation by electroplating and the flip-chip process. In contrast to commercially available hybrid arrays, the indium solderbump technology is applied to the III-V array only and not to the silicon readout. This causes specific requirements to the IIIV metallization sequence prior to electroplating in order to obtain proper reflow. Two different silicon postprocessing schemes are described. Arrays of 128*128, 256*256 and 320*256 In(Ga)As and InAsSb photovoltaic infrared detectors have been integrated with dedicated in-house and commercial readout using this process. The feasibility of achieving 10 (mu)m hybrid integration pitch is also shown.