Graph partitioning applied to the logic testing of combinational circuits Original Research Article

Logical testing of integrated circuits is an indispensable part of their fabrication. Exhaustive testing of a VLSI (very large scale integration) circuit, which can detect all its faults, is impractical due to the complexity of such circuits and the number of input patterns that have to be applied. A circuit with n inputs would require 2n different input patterns to be exhaustively tested. To overcome this problem when n is larger than about 20, the circuit can be partitioned into subscircuits each with fewer inputs, which can then be tested exhaustively. This procedure, known as the pseudo-exhaustive testing has a better fault coverage than classical methods. In this paper we present a graph partitioning model for the problem of partitioning a combinational VLSI circuit represented by a directed acyclic graph. However, any direct approach to finding an optimal solution to the graph partitioning problem will require an inordinate amount of computation. Therefore, we propose a polynomial complexity algorithm, composed of two phases, which has been tested with benchmark ISCAS circuits.