Processor-based turbo interleaver for multiple third-generation wireless standards

A software turbo interleaver running on a SIMD processor is presented for a turbo decoder supporting multiple 3G wireless standards. To hide the timing overhead of interleaver changing, the interleaver generation is split into two parts, preprocessing and incremental on-the-fly generation. Applying the proposed approach, we implemented a W-CDMA and cdma2000 interleaver that generates one interleaved address per cycle and occupies 10% area of the ROM implementation.