A technique for nonlinearity self-calibration of DLLs

The on-chip nonlinearity self-calibration of a CMOS all-digital shunt-capacitor-based delay-locked delay-line is achieved by first measuring the nonlinearity of each delay-cell by means of a statistical test, and then individually correcting the cell delay mismatch according to the test results. An iterative calibration algorithm has been developed and a fully-digital circuit efficiently implementing the calibration procedure has been designed. Simulation results show the feasibility of the technique and a significant reduction of the delay-line maximum nonlinearity down to values that can be below 1%.